1. Field of the Invention
The invention relates in general to integrated circuit testing and in particular to a method for performing both functional and delay fault testing on an integrated circuit.
2. Description of Related Art
A digital integrated circuit (IC) typically includes a large number of logic blocks communicating with one another through clocked devices such as registers and flip-flops. For example FIG. 1 illustrates a simple integrated circuit 10 including a set of six primary inputs PI1-PI6 for receiving input signals, a set of logic blocks L1-L6 for performing logic operations on the input signals to produce a single primary output signal P0. A set of clocked devices, in this example flip-flops F1-F5, are included in signal paths between logic blocks L1-L6 to synchronize state changes in signals passing between the logic blocks to edges of a clock signal CLK that clocks all flip-flops. Although for simplicity IC 10 is illustrated as including only a few input, output and clock signals, logic blocks and clocked devices, a typical IC will have many more primary inputs and outputs, logic blocks and clocked devices. Also, though in this simple example, all clocked devices F1-F5 are clocked by the same clock signal CLK, many ICs employ two or more clock signals of varying phases to clock clocked devices.
Functional Testing
As illustrated in FIG. 2, an IC tester 12 performs a functional test on IC 10 by applying signal patterns to the IC's primary inputs PI1-PI6 and clock input CLK and by monitoring the IC's primary output signal PO to determine whether it behaves as expected. When IC 10 is unpackaged, tester 12 can employ probes to also access and monitor some of the IC's internal signals, such as signals S1-S5. IC testers are typically “cycle based” in that they organize a test into a succession of test cycles of uniform length, and carry out test activities during each test cycle. During each test cycle, tester 12 may change the state of test signals supplied to IC 10 input terminals or sample IC output signals to determine whether they are of expected states. A typical tester 12 is programmed to generate a separate test vector (variously called a functional, operation or behavioral vector) for each IC input/output (IO) terminal prior to the start of each test cycle indicating the test activity to be carried out at the IC IO terminal. The vectors are typically derived from data produced by a circuit simulator indicating the expected response of IC's internal and output signals to a particular input signal pattern.
The maximum frequency at which tester 12 can test IC 10 depends in part on the period of the test cycle. A shorter test cycle period permits a higher test cycle frequency. Since a tester must supply and process a set of vectors at the start of each test, the maximum frequency at which it can test an IC is often limited by the maximum rate at which it can generate and process test vectors. The test frequency also depends on the number of test activities per cycle each vector can define. The frequency at which tester 12 can test IC 10 of FIG. 1 is limited by the frequency at which it can generate the CLK signal. If a vector can define only a single test signal state change per test cycle, then a full clock signal cycle, including both a rising and falling pulse edges, will require two test cycles. In such case the maximum test cycle frequency will be 1/2P, where P is the tester's minimum possible test cycle period in nanoseconds. Tester 12 can test IC 10 at a higher test frequency when a vector can define more than one activity per test cycle at any given IC IO terminal. For example, when a vector can define up to two activities per test cycle, it can tell tester 12 to drive the CLK signal high at one point during a test cycle and to drive it low at another point during a test cycle. Since such a tester 12 would need only one test cycle period to produce a complete CLK signal cycle, tester 12 will be able to test IC 12 at a maximum test frequency of 1/P. When a vector can define up to four activities per IC IO terminal per test cycle, tester 12 could test IC 10 at a maximum test frequency of 2/P.
The cost of an IC tester is an increasing function of its maximum test frequency. When a fast, but relatively expensive, tester 10 performs an “at-speed” functional test by clocking IC 10 at its intended operating frequency, timing-related defects in the IC can cause detectable errors in the monitored IC signals. Thus an at-speed test can test both the logic and the timing of an IC. A relatively inexpensive, but slow, tester 12 can perform a low-speed functional test by clocking IC 10 at a lower frequency than its intended operating frequency. However although a low-speed functional tester 12 can verify the logic of logic blocks L1-L6, it cannot determine whether the logic blocks and their interconnecting paths have sufficiently low path delays to enable them to operate when the IC is clocked at its intended operating frequency. The need for high-speed testing has grown as the operating frequencies of IC continue to increase, but it has become increasingly more difficult to design testers capable of performing at-speed functional tests.
Scan Chains
An IC's clocked devices (registers, flip-flops, etc) can be organized into one or more scan chains that enable an IC tester to directly read and set the states of the output signals of those devices even when it does not have direct access to those signal. FIG. 3 illustrates a simplified IC 14 similar to IC 10 of FIG. 1 except that its flip-flops F1-F5 are interconnected through a set of multiplexers M1-M5 to form a scan chain. During normal IC operation, the scan enable signal SE control input to multiplexers M1-M5 are de-asserted (set to a logical 0) so that multiplexers M1-M5 connect the outputs of logic blocks L1-L5 to the inputs of flip-flops F1-F5, respectively. During a scan mode of operation, an IC tester can assert (set to a logical 1) the SE control signal so that multiplexers M1-M5 connect the inputs and outputs of flip-flops F1-F5 in series between a scan input terminal SI and a scan output terminal SO. In the scan mode, successive edges of the CLK signal shift serial data arrive from the IC tester on scan input terminal SI into flip-flips F1-F5 and shift data representing the output signals S1-S5 of flip-flops F1-F5 out of the IC via scan output terminal SO. Thus an IC tester can use the scan mode to set the S1-S5 signals to desired states and/or to read the states of the S1-S5 signals.
Scan Dump Testing
As shown in FIG. 4, an IC tester 16 accessing the logic 18 of IC 14 via its primary input, output and clock signals and accessing the IC's scan chain via its SE, SI and SO terminals can halt a functional test and carry out a “scan dump” using scan chain 20 to read the states of the output signals S1-S5 of flip-flops L1-L6 of FIG. 3.
FIG. 5 illustrates timing relationships between the clock signal CLK signal and the scan enable signal. During a functional test, when IC tester 16 is supplying a pattern of input signals PI1-PI6 to logic 18 and monitoring the primary output signal P0, the tester holds the scan enable signal low so that the combinatorial logic 18 operates in its normal mode. At time T1, tester 16 asserts scan enable signal SE to place IC 14 in its scan mode. Thereafter, successive edges of clock signal CLK serially shift out data representing states of flip-flop output signals S1-S5.
When tester 16 performs low-speed functional test, the tester can avoid having to restart the test from the beginning after performing a scan dump during any test cycle by reloading the dumped scan data back into the IC before starting the next test cycle. Scan dumps are not performed in in an at-speed test because shifting to scan mode disrupts circuit timing. However the low-speed function test may not detect any of the errors if they result from excessive propagation delays in the logic producing signal.
Error Diagnosis Using Scan Dump Testing
FIG. 6 illustrates various pass/fail states of signals of IC 14 as detected by tester 16 of FIG. 4 during several cycles of a test. Each small box represents a result of a comparison between a signal's actual state and its expected state during a clock cycle. An empty box indicates that the corresponding signal was of its expected state during the corresponding clock cycle. A solid black box indicates that the corresponding signal was of an unexpected state during the corresponding clock cycle and that the signal state error was a “initial error” in the sense that the error in the signal was caused by a defect in the logic block controlling the signal and not by an error in any input signal to that logic block. A box containing an X indicates that the corresponding signal was of an unexpected state during the corresponding clock cycle, and that the signal error propagated from an earlier error in another signal. A test engineer wants to know which signals may be of unexpected states during any given test cycle because that information can help the test engineer to determine which logic blocks may contain logic or path delay errors. However, the test engineer may not be able to deduce the cause of every signal error from the tester output data.
During an at-speed functional test in which tester 16 can observe only the IC's primary output signals P0, it will report an error in that signal at clock cycle 221. However it does not report the unobservable errors in signals S2, S3 and S5 at cycles 219 and 220. The test engineer might want to know whether the error in PO at cycle 221 was an original error occurring in logic block L6 during cycle 221 or a propagation error resulting from an error in some other logic block at an earlier test cycle. Suppose the test engineer reprogrammed the tester to repeat the test from the first clock cycle, performing a first scan dump at cycle 220. When the scan data indicates there are errors in signals S3 and S5 at cycle 220, the test engineer could reprogram the tester to repeat the test from the first clock cycle, performing a second scan dump at test cycle 219. Since the scan data indicates an error in signal S2, the test engineer might reprogram the tester to repeat the test from the first clock cycle, performing a third scan dump at test cycle 218. Since there are no errors at test cycle 218, the test engineer ceases the scan process.
At this point the tester output data will tell the test engineer that errors occurred in signal S2 at cycle 219, in signals S3 and S5 at cycle 220, and in signal P0 at cycle 221. The test engineer will be able to infer that the error in signal S2 at cycle 219 was an original error, but will not be able to determine from the test result data whether that error was due to a logic error in logic block L2 of FIG. 3 or was due to a path delay error in logic block L2. Also, the test engineer will not be able to directly determine from the test result data whether the errors in signals S3 and S5 at cycle 220 or in signal P0 at cycle 221 were propagation errors or whether they were original errors resulting from logic faults or path delay errors in the logic blocks that generate those signals.
U.S. Patent Publication 2002/0112208 A1, published Aug. 15, 2002 for an application filed Jan. 9, 2001 by Kakizawa et al describes a generally similar approach scan dump testing.
ATPG Scan Testing
Tester 16 of FIG. 4 can use the scan chain 20 to directly set the states of the IC's internal signals that are accessible to the scan chain. In automatic test pattern generation (ATPG) scan testing, as illustrated in the timing diagram of FIG. 7, tester 16 drives the shift enable signal high during a first “shift window” spanning several clock cycles between times T1 and T2 to enable scan chain 20 and then uses the scan chain to serially shift data into flip-flops F1-F5 (FIG. 3), thereby driving signals S1-S5 to a desired pattern of states. Tester 16 then drives the shift enable signal SE low between times T2 and T3 to disable scan chain 20 and (optionally) inhibits a next clock signal pulse to allow the effects of any state changes in signals S1-S5 to propagate through logic blocks L1-L5 of FIG. 3. An edge of a next CLK signal pulse at time clocks the outputs of logic blocks L1-L5 into flip-flops F1-F5 so that at time T3, the outputs of flip-flops F1-F5 reflect the response of logic blocks L1-L5 to the S1-S5 input signal pattern supplied during the first shift window. During a second shift widow between times T3 and T4, tester 16 drives the shift enable signal high to enable scan chain 20 and uses it to shift out data representing states of signals S1-S5. During the second shift window between times T3 and T4, tester 16 also shifts in new pattern data to set the S1-S5 signals to new states for a next capture procedure between times T4 and T5. The test vectors for programming a tester to carry out ATPG scan testing are typically produced by ATPG tools that analyze a circuit model to determine how to test each individual logic block to detect particular types of faults within that logic block.
For IC 14 of FIG. 3, ATPG scan testing can allow tester 16 to directly control the states of inputs S1, S2, S3 and S6 to logic blocks L3, L5 and L5 rather than indirectly controlling them by controlling only states of primary input signal PI1-PI6, thereby making it easier to test each block for its response to various input signal patterns. The tester can repeatedly alternate between scan and capture procedures to determine the response of each logic block to various patterns of input signals. One drawback to the type of ATPG scan testing illustrated in FIG. 7 is that while it allows a tester to detect “stuck-at” faults and other logic errors in an IC's logic blocks, it does not allow the tester to detect timing errors because the tester allows more time between times T2 and T3 and between times T4 and T5 for signals to propagate through the logic blocks than would be permitted when the IC is operating at its normal operating frequency, as for example, in an at-speed functional test.
Delay Fault ATPG Scan Testing
FIG. 8 illustrates timing relationships between the clock CLK and scan enable signals when tester 16 of FIG. 4 performs a modified form of ATPG scan testing that can detect delay faults. During a first scan procedure spanning times T1 through T2, tester 16 drives the shift enable signal high to enable scan chain 20 and uses it to serially shift data into flip-flops F1-F5 to drive signals S1-S5 of FIG. 3 to a desired pattern of states. Tester 16 then drives the shift enable signal SE low at time T2 to disable scan chain 20. During a first capture procedure spanning times T2-T5, tester 16 delays a next edge of clock signal CLK for a time following time T2 to allow the effects of any state changes in signals S1-S5 to propagate through logic blocks L1-L5 of FIG. 3. An edge of a next CLK signal pulse at time T3 clocks the outputs of logic blocks L1-L5 into flip-flops F1-F5 so that the outputs of flip-flops F1-F5 reflect the response of logic blocks L1-L5 to the S1-S5 input signal pattern supplied during the first scan procedure. A next clock signal edge at time T4 again clocks the outputs of logic blocks L1-L5 into flip-flops F1-F5 so that at time T5, the outputs of flip-flops F1-F5 reflect the response of logic blocks L1-L5 to the S1-S5 input signal pattern following the first capture procedure. During a second scan procedure starting at time T5, tester 16 drives the shift enable signal high to enable scan chain 20 and uses it to shift out data representing the second captured states of signals S1-S and to shift new data into flip-flops F1-F5 to drive signals S1-S5 of FIG. 3 to a next desired pattern of states. Tester 16 then drives the shift enable signal SE low at time T6 to disable scan chain 20. During a second capture procedure spanning times T6-T9, tester 16 produces a CLK signal edge at time T7 to clock the outputs of logic blocks L1-L5 into flip-flops F1-F5 so that the outputs of flip-flops F1-F5 reflect the response of logic blocks L1-L5 to the S1-S5 input signal pattern supplied during the second scan procedure. A clock signal edge at time T8 again clocks the outputs of logic blocks L1-L5 into flip-flops F1-F5 so that at time T9, the outputs of flip-flops F1-F5 reflect the response of logic blocks L1-L5 to the S1-S5 input signal pattern following the second capture procedure.
Tester 16 adjusts the delay between CLK signal edges occurring at times T3 and T4 and between CLK signal edges occurring at times T7 and T8 so that the logic blocks L1-L5 have a controlled amount of time to respond to changes in their input signal states between the two clock signal edges. An excessive path delay in any logic block L1-L5 can cause an error in the state of the output signal of that block reflected by the scan data captured during the second shift window.
A low speed tester that is not fast enough to perform an at-speed functional test can use this technique to perform delay testing even though the period between test cycles is longer than the period between times T3 and T4, provided that the tester can control the timing of CLK signal edges within each test cycle with high resolution. FIG. 8 shows how tester 16 can position each CLK signal pulse within a test cycle. When tester 16 produces the CLK signal pulse starting at time T3 near the end of test cycle 6 and produces the CLK signal pulse starting at time T4 near the beginning of a test cycle 7, the period T4-3 between clock signal edges is much smaller than the period of each test cycle. The “idle” test cycles 5 and 12 in which no CLK signal pulses occur are provided to ensure the IC logic settles to steady state before the delay default test begins at times T3 and T7. In some cases the idle cycles can be omitted.
At-speed functional testing is advantageous because it directly verifies that an IC behaves in the manner predicted by a circuit simulator and can detect timing errors. However when at-speed functional testing is not practical, test engineers can employ low-speed functional testing to verify that the IC logically behaves in the predicted manner and can employ delay fault ATPG scan testing to determine whether path delays within the IC's logic blocks are within acceptable limits. The drawback to this approach is that developing and carrying out two different types of tests on an IC can be time-consuming.